TI device's hardware ECC implementation calculates ECC on 512 byte data chunks. But the block is not really bad. The NAND flash is specified such that the first block only requires 1-bit ECC correction. In this scenario, if more than 4 errors are detected, the errors can't be corrected.
However, we have no idea which of the 511 chunks of data contains an error in its bit #0. Like last night, my brain demanded to understand how to design an ECC algorithm (software program but possibly FPGA circuitry eventually) to implement the kind of ECC appropriate for disk drives. For 2048 bytes page, 64 bytes of redundant data will be generated. (In current TI devices, the ECC data is generated for every 512 bytes) There are two ways to store YAFFS doesn't appear to be in the GPL kernel dist, and I don't really trust the defconfig, so I hesitate to base any assumptions on that source...
If you are using mkyaffs to initialise a partition then I suggest you start off working with an empty partition. When such a chunk write error occurs, it could be after some number of good chunks in the erase block have been written. BTW, I don't naturally "think in math", so please don't point me to math papers! Various layouts are supported for the spare bytes.
Aha! It could probably be optimized a bit to error out quicker, but I don't think that is actually a performance concern here. So if bit #0 of the code7 ECC we read back from disk differs from the code7 ECC we compute from the read data, we know that bit #0 error is have a peek here Memories compatible to MMC 4.2 and SD 2.1 will work seamlessly with these processors.
If you have multi-bit correcting data then it makes sense to modify what the driver reports. Suppose I have a high ECC strength flash (20-bit correction?) but gf_len is 14. Excellent! This appears to still be in place in the latest release...
My approach is to compute ten 64-bit ECC codes from the 4096 bytes of data. http://lists.infradead.org/pipermail/linux-mtd/2014-March/052474.html more stack exchange communities company blog Stack Exchange Inbox Reputation and Badges sign up log in tour help Tour Start here for a quick overview of the site Help Center Detailed thanks Xiaoguang -----Original Message----- From: [email protected] [mailto:[email protected]] On Behalf Of Charles Manning Sent: 2011年9月21日 13:22 To: [email protected] Subject: Re: [Yaffs] yaffs handle chunk error calling On Tuesday 20 September 2011 14:47:08 Derek Top dtaubert Topic Author Posts: 97 Joined: Wed Sep 15, 2004 3:06 pm Quote #4 Tue Oct 19, 2004 12:56 pm These errors are coming from YAFFS (output below
As per general calculations  OOB Area (spare region) >= B * ( Page_Size / 512 ) + 2 + FileSystem_metadata where B = 8 bytes for BCH4 B = 14 just under 1KB, which effectively limits it to 512 bytes + ECC + some optional auxiliary data. Hence choice of ECC scheme is limited by size of OOB/spare region available per page of the NAND. This is because a real erased page is full of 0xFF(maybe also has > several bitflips), while a page contains the 0xFF data will definitely > has many bitflips in the
and we count the bitflips again, assume it is N2. > (We read out the whole page, not just a chunk, this makes the check > more strictly, and make the We can still use > it since it only has 4 times of fixed ECC error happened. Given that /dev/mtdblock/2 is in active use by the system, what's the expected MTTF for the onboard flash? I presume (based upon the above info) that these blocks were written bad at the time of my last firmware upgrade.
GPMC on some devices has an erratum affecting BCH-4 calculation. I think it could be thrown out for simplicity in the generic case (e.g., in my sample pasted below). > + > + /* > + * Read out the whole Please post only comments about the article Raw NAND ECC here.
The particular BCH family used by GPMC and ELM however requires that the data size including ECC bits is at most 8191 bits, i.e. Does ECC have to be calculated on a 512-byte data chunk? Each zero bit in the chunk # of the error is a code# where we did not find an error, and each one bit in the chunk # of the error Now, if we see 10 bitflips in an erased page, we will return false here, saying this page was not erased.
Extra memory (called the "spare memory area" or "spare bytes region") is provided at the end of each page in NAND which could be used to store the ECC. Thanks in advance for any clues! We now know exactly where the error is in our 4096-byte sector --- at bit #0 of 64-bit chunk #185. Anyway, I'll describe what my brain dreamed up in my sleep, and ask anyone to explain how this kind of ECC actually should be done, and how much better are conventional
Now we ask ourselves, what can code7 tell us? Top dtaubert Topic Author Posts: 97 Joined: Wed Sep 15, 2004 3:06 pm Quote #3 Tue Oct 19, 2004 12:30 pm Is the onboard flash NAND or NOR based? When we find an error in bit #0 of code4, we know the error must be somewhere in chunks 176-191. The ECC in the device (OMAP35x,AM35x,AM/DM37x) must then be disabled after boot (ie in XLOADER for example) Then thebuilt-in ECC in NAND device can be enabled (ie again in XLOADER) Note:
Before I woke up, I was trying to figure out how to handle two bursts per track, but woke up defeated. When a bit in the readback ECC matches the same bit in the ECC we computed from the read data, we generate a 0, otherwise we generate a 1 (readback-ECC XOR For some of the NANDs, the built in ECCcorrection defaults to an "off state" upon power-on of the NANDdevice. How this works is becoming obvious.
When we find NO error in bit #0 of code2, we know the error must be somewhere in chunks 184-187.